1. Field of the Invention
The present invention relates to a dual gate cascade amplifier. More particularly, the present invention relates to a dual gate cascade amplifier having gates with adjustable widths.
2. Description of the Related Art
A conventional cascade amplifier has a structure in which a drain of a common source metal oxide semiconductor field effect transistor (MOSFET) is connected to a source of a common drain MOSFET. FIG. 1A illustrates a vertical cross-sectional view of a conventional cascade amplifier. FIG. 1B is an equivalent circuit diagram of the conventional cascade amplifier of FIG. 1A. Referring to FIGS. 1A and 1B, the conventional cascade amplifier includes two separate transistors, i.e., first and second transistors T1 and T2. The first and second transistors T1 and T2 have sources S1 and S2, respectively, drains D1 and D2, respectively, and gates G1 and G2, respectively. A channel C1 is disposed between the source S1 and drain D1 of the first transistor T1, and a channel C2 is disposed between the source S2 and drain D2 of the first transistor T2. Gate G1 is formed over the source S1, the channel C1, and the drain D1 of the first transistor T1 with a gate insulation layer (not shown) interposed therebetween. Gate G2 is formed over the source S2, the channel C2, and the drain D2 of the second transistor T2 with a gate insulation layer (not shown) interposed therebetween.
Gain of the conventional cascade amplifier can be controlled by controlling a voltage applied to the gate G2 of the second transistor T2. In addition, the conventional cascade amplifier has little gain loss but high circuit stability because it can reduce capacitance caused by Miller's effect and thus can prevent a feedback of an output signal. However, the conventional cascade amplifier may cause noise due to the resistance and parasitic capacitance of a substrate when using frequencies in a radio-frequency (RF) band. However, the characteristics of the conventional cascade RF amplifier may be adversely affected by substrate resistance and parasitic capacitance Rsub.
In a complementary metal oxide semiconductor (CMOS) structure, noise most typically occurs between the drain D1 of the first transistor T1 and the source S2 of the second transistor T2. In order to reduce noise, which is partly responsible for substrate loss in the CMOS structure, the substrate resistance may be increased, or portions of the CMOS structure, in which noise caused by the parasitic capacitance is likely to occur, (hereinafter, referred to as a noise source), may be removed. A dual gate transistor is one type of transistor, from which the noise region has been removed.
In the dual gate transistor, two gates share one channel disposed between a source and a drain. A dual gate transistor can be obtained by removing the drain D1 of the first transistor T1 and the source S2 of the second transistor T2 from the conventional cascade amplifier of FIG. 1.
FIG. 2A illustrates a vertical cross-sectional view of a conventional dual gate cascade amplifier, in which two gates share one channel. FIG. 2B is an equivalent circuit diagram of the dual gate cascade amplifier of FIG. 2A. Referring to FIGS. 2A and 2B, two gates G1 and G2 share one channel C between a source S1 and a drain D2.
The conventional dual gate cascade amplifier, unlike the conventional cascade amplifier of FIGS. 1A and 1B, in which the drain D1 of the first transistor T1 and the source S2 of the second transistor T2 serve as noise sources, does not have any noise sources and has a structure in which the two gates G1 and G2 share a common channel C. The conventional dual gate cascade amplifier can reduce a minimum noise figure NFmin by about 0.7 dB. However, the conventional dual gate cascade amplifier has limited applicability.
FIG. 3 is a layout diagram of a conventional multi-finger dual gate cascade amplifier. Referring to FIG. 3, due to the structure of the conventional multi-finger dual gate cascade amplifier, transistors in the multi-finger dual gate cascade amplifier are necessarily formed to have the same total gate width. In order to optimize the noise and linearity characteristics of a cascade amplifier, it is necessary to adjust the total gate width of each transistor in the cascade amplifier. However, the noise and linearity characteristics of the conventional multi-finger dual gate cascade amplifier cannot be optimized because the total gate widths of the transistors in the conventional multi-finger dual gate cascade amplifier are not adjustable.
In addition, since the conventional multi-finger dual gate cascade amplifier, as shown in FIG. 3, does not have noise sources, such as the drain D1 of the first transistor T1 of FIG. 1 and the source S2 of the second transistor T2 of FIG. 1, a passive device for matching noise or power of one transistor with noise or power of another transistor, for example, an inductor, a capacitor, or a register, cannot be disposed between the transistors. Accordingly, even though the conventional multi-finger dual gate cascade amplifier can minimize noise caused by substrate resistance, it still has very limited applicability.